IBPS IT OFFICER MCQ – 73

 IT OFFICER

1. The fetch and execution cycles are interleaved with the help of?
a) Modification in processor architecture
b) Clock
c) Special unit
d) Control unit

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Answer b) Clock

2. The periods of time when the unit is idle is called as?
a) Stalls
b) Bubbles
c) Hazards
d) Both a and b

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Answer d) Both a and b

The stalls are a type of hazards that affect a pipelined system

3. The addressing mode, where you directly specify the operand value is ?
a) Immediate
b) Direct
c) Definite
d) Relative

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Answer a) Immediate

4. The Input devices can send information to the processor?
a) When the SIN status flag is set
b) When the data arrives regardless of the SIN flag
c) Neither of the cases
d) Either of the cases

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Answer a) When the SIN status flag is set

5. ISP stands for?
a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure

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Answer a) Instruction Set Processor

6. To reduce the memory access time we generally make use of?
a) Heaps
b) Higher capacity RAM’s
c) SDRAM’s
d) Cache’s

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Answer
d) Cache’s

7. MFC stands for?
a) Memory Format Caches
b) Memory Function Complete
c) Memory Find Command
d) Mass Format Command

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Answer b) Memory Function Complete

8. The addressing mode which makes use of in-direction pointers is?
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode

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Answer a) Indirect addressing mode

9. The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy?
a) True
b) False

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Answer a) True

10. The pipelining process is also called as?
a) Superscalar operation
b) Assembly line operation
c) Von Neumann cycle
d) None of the mentioned

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Answer b) Assembly line operation

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A Moorthy

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